Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement
Abstract
Purpose
The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA).
Design/methodology/approach
The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time.
Findings
Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms.
Originality/value
The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.
Keywords
Citation
Ouni, B. and Mtibaa, A. (2012), "Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement", Microelectronics International, Vol. 29 No. 2, pp. 101-107. https://doi.org/10.1108/13565361211237707
Publisher
:Emerald Group Publishing Limited
Copyright © 2012, Emerald Group Publishing Limited