Novel layout technique for on‐chip inductance minimization

Abstract

Purpose

The purpose of this paper is to minimize on‐chip inductance effect for modern very large‐scale integration (VLSI), ultra large‐scale integration (ULSI) systems.

Design/methodology/approach

As operating frequency increases, parasitic inductance has become a major concern for electronic design on both delay and coupling noises. The impacts of on‐chip inductance are strongly associated with higher frequency operation, denser interconnect geometry, reductions of resistance, and capacitance of interconnects. The paper presents a novel layout technique – opposing inter‐digitating routing, to generate magnetic fields in opposing directions; consequently, effective magnetic field is minimized, or inductance effect is reduced. To prove the effectiveness of these approaches, 3D field solver FastHenry is used to extract inductance data and verify the results.

Findings

Verification shows that this proposed method gives more than ten times reduction in self‐inductance while mutual inductance reduces even faster, without incurring any area and resource penalty.

Originality/value

The proposed technique can be used effectively to minimize inductance effects in the design of modern interconnect structures. This technique is shown to be highly effective for inductance reduction in wide signal buses which are used frequently in global buses, critical data path or clock distribution networks of VLSI and ULSI systems.

Citation

Dao, V.T.S., Etoh, T.G., Tanaka, M. and Akino, T. (2009), "Novel layout technique for on‐chip inductance minimization", Microelectronics International, Vol. 26 No. 3, pp. 3-8. https://doi.org/10.1108/13565360910981508