Modeling of jitter in bang‐bang clock and data recovery circuits

Abstract

Purpose

Bang‐bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized.

Design/methodology/approach

The presented method is enough to be used for designing the BBCDR loop parameters.

Findings

In this paper, jitter characteristics of the BBCDR are characterized. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The analysis is verified using behavioral simulations in MATLAB. Simulation results show that good conformance between analytical equations and simulation results.

Originality/value

The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero.

Citation

Adrang, H. and Saleh Ghoreishi, S. (2013), "Modeling of jitter in bang‐bang clock and data recovery circuits", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 32 No. 3, pp. 1151-1168. https://doi.org/10.1108/03321641311309067